74ACT652 データシートの表示（PDF） - Fairchild Semiconductor

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74ACT652

Transceiver/Register

Fairchild Semiconductor 

Functional Description

In the transceiver mode, data present at the HIGH imped-

ance port may be stored in either the A or B register or

both.

The select (SAB, SBA) controls can multiplex stored and

real-time.

The examples in Figure 1 demonstrate the four fundamen-

tal bus-management functions that can be performed with

the Octal bus transceivers and receivers.

Note A: Real-Time

Transfer Bus B to Bus A

Data on the A or B data bus, or both can be stored in the

internal D-type flip-flop by LOW to HIGH transitions at the

appropriate Clock Inputs (CPAB, CPBA) regardless of the

Select or Output Enable Inputs. When SAB and SBA are in

the real time transfer mode, it is also possible to store data

without using the internal D-type flip-flops by simulta-

neously enabling OEAB and OEBA. In this configuration

each Output reinforces its Input. Thus when all other data

sources to the two sets of bus lines are in a HIGH imped-

ance state, each set of bus lines will remain at its last state.

Note B: Real-Time

Transfer Bus A to Bus B

OEAB OEBA CPAB CPBA SAB

L

L

X

X

X

SBA

L

Note C: Storage

OEAB OEBA CPAB CPBA SAB

H

H

X

X

L

SBA

X

Note D: Transfer Storage

Data to A or B

OEAB

X

L

L

OEBA

H

X

H

CPAB

X

CPBA

X

SAB

X

X

X

SBA

X

X

X

OEAB OEBA CPAB CPBA SAB

H

L H or L H or L H

SBA

H

FIGURE 1.

3

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