M66305AFP データシートの表示（PDF） - MITSUBISHI ELECTRIC
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M66305AFP Datasheet PDF : 10 Pages
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MITSUBISHI 〈DIGITAL ASSP〉
M66305AP/AFP
TOGGLE LINE BUFFER
TIMING CONDITIONS (Ta = –10˚C ~ 70°C, VCC = 5V±10% and GND = 0V unless otherwise noted)
Symbol
Parameter
Limits
Min.
Typ.
Max.
tw±(SIC)
Input clock pulse width (Note 2)
30
43*
tw±(SOC)
Output clock pulse width (Note 2)
50
tw(T)
Toggle signal input pulse width
150
tw(RES)
Reset input pulse width
100
tw(CR1)
Write counter reset input pulse width
100
tw(CR2)
Read counter reset input pulse width
100
tsu(SID-SIC)
Input data setup time before input clock
25
th(SIC-SID)
Input data hold time after input clock
0
tsu(ICE-SIC)
Input clock enable setup time before input clock
25
th(SIC-ICE)
Input clock enable hold time after input clock
0
tsu(CS-SIC)
Chip select setup time before input clock
150
th(SIC-CS)
Chip select hold time after input clock
100
tsu(OCE-SOC)
Output clock enable setup time before output clock
25
th(SOC-OCE)
Output clock enable hold time after output clock
0
tsu(CS-SOC)
Chip select setup time before output clock
150
th(SOC-CS)
Chip select hold time after output clock
100
tsu(CS-T)
Chip select setup time before toggle signal input
100
th(T-CS)
Chip select hold time after toggle signal input
100
th(SIC-T)
Toggle signal hold time after input clock
100
trec(T-SIC)
Input clock recovery time after toggle signal input
150
th(SOC-T)
Toggle signal hold time after output clock
100
trec(T-SOC)
Output clock recovery time after toggle signal input
150
tsu(CS-CR1)
Chip select setup time before write counter reset
100
th(CR1-CS)
Chip select hold time after write counter reset
100
tsu(CS-CR2)
Chip select setup time before read counter reset
100
th(CR2-CS)
Chip select hold time after read counter reset
100
trec(R-SIC/SOC)
Input and output clock recovery time after reset
100
trec(CR1-SIC)
Input clock recovery time after write counter reset
150
trec(CR2-SOC)
Output clock recovery time after read counter reset
150
Note 2 To satisfy switching characteristic fmax = 10 MHz (frequency: 100ns), the condition shown below should be met: 100 ns ≤ (tW+) + (tW–)
SWITCHING CHARACTERISTICS (Ta = –10˚C ~ 70°C, VCC = 5V±10% and GND = 0V)
Symbol
Parameter
Test conditions
Limits
Min.
Typ.
Max.
tc(SIC)
Input clock cycle time
100
tc(SOC)
Output clock cycle time
100
CL=50pF
36
tPLH(SOC-SOD)
CL=150pF
40
Propagation time between input clock and output data
CL=50pF
36
tPHL(SOC-SOD)
CL=150pF
40
CL=50pF
75
tPHL(SIC-BF)
Propagation time between input clock and BF
CL=150pF
85
CL=50pF
75
tPHL(SOC-INT)
Propagation time between output clock and INT
CL=150pF
85
tPLH(T-BF)
Propagation time between toggle signal input and BF
100
tPLH(T-INT)
Propagation time between toggle signal input and INT
100
tPLH(R-BF)
Propagation time between reset input and BF
100
CL=150pF
tPLH(R-INT)
Propagation time between reset input and INT
100
tPHL(CR1-BF)
Propagation time between write counter reset and BF
100
tPLH(CR2-INT)
Propagation time between read counter reset and INT
100
Note 3 AC test waveform ;
Input pulse level: 0V ~ 3V
Input pulse rise time: 6ns
Input pulse fall time: 6ns
Test voltage ;
Input voltage: 1.3V
Output voltage: 1.3V
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*: Ta=25˚C
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6
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