DS2175 データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated

部品番号

コンポーネント説明

一致するリスト

DS2175

T1/CEPT Elastic Store

Dallas Semiconductor -> Maxim Integrated 

DS2175

PCM BUFFER

The DS2175 utilizes a 2–frame buffer to synchronize in-

coming PCM data to the system backplane clock. Buff-

er depth is mode–dependent; 2.048 MHz to 2.048 MHz

applications utilize 64 bytes of buffer memory, while all

other modes are supported by 48 bytes. The buffer

samples data at RSER on the falling edge of RCLK.

Output data appears at SSER and is updated on the ris-

ing edge of SYSCLK. The buffer depth is constantly

monitored by onboard contention logic; a “slip” occurs

when the buffer is completely emptied or filled. Slips au-

tomatically recenter the buffer to a one–frame depth and

always occur on frame boundaries.

DATA FORMAT

Data is presented to, and output from, the elastic store in

a “framed” format. A rising edge at RMSYNC and

SFSYNC establishes frame boundaries for the receive

and system sides. North American (T1) frames contain

24 data channels of 8 bits each and an F–bit (193 bits

total). European (CEPT) frames contain 32 data chan-

nels (256 bits). The frame rate of both systems is 8 KHz.

RMSYNC and SFSYNC do not require a pulse at every

frame boundary; if desired, they may be pulsed once to

establish frame alignment. Internal counters will then

maintain the frame alignment and may be reinforced by

the next rising edge at RMSYNC and/or SFSYNC.

SLIP CORRECTION CAPABILITY

The 2–frame buffer depth is adequate for T–carrier and

CEPT applications where short term jitter synchroniza-

tion, rather than correction of significant frequency dif-

ferences, is required. The DS2175 provides an ideal

balance between total delay (less than 250 microse-

conds at its full depth) and slip correction capability.

BUFFER RECENTERING

Many applications require that the buffer be recentered

during system power–up and/or initialization. Forcing

ALN low recenters the buffer on the occurrence of the

next frame sync boundary. A slip will occur during this

recentering if the buffer depth is adjusted. If the depth is

presently optimum, no adjustment (slip) occurs.

SLIP REPORTING

SLIP is held low for 65 SYSCLK cycles when a slip oc-

curs. SLIP is an active–low, open collector output. FSD

indicates slip direction. When low (buffer empty) a

frame of data was “repeated” at SSER during the pre-

vious slip. When high (buffer full), a frame of data was

“deleted”. FSD is updated at every slip occurrence.

BUFFER DEPTH MONITORING

SMSYNC is a system side output pulse which indicates

system side multiframe boundaries. The distance be-

tween rising edges of RMSYNC and SMSYNC indi-

cates the current buffer depth. Impending slip condi-

tions may be determined by monitoring RMSYNC and

SMSYNC real time. SMSYNC is held high for 65

SYSCLK periods.

CLOCK SELECT

Receive and system side clock frequencies are inde-

pendently selectable by inputs RCLKSEL and

SCLKSEL. 1.544 MHz is selected when RCLKSEL

(SCLKSEL) = 0; 2.048 MHz is selected when RCLKSEL

(SCLKSEL) = 1. In 1.544 MHz (receive) to 1.544 MHz

(system) applications, the F–bit position is passed

through the receive buffer and presented at SSER im-

mediately after the rising edge of the system side frame

sync. The F–bit position is forced to 1 in 2.048 MHz to

1.544 MHz applications. No F–bit position exists in

2.048 MHz system side applications.

PARALLEL COMPATIBILITY

The DS2175 is compatible with parallel and serial back-

planes. Channel 1 data appears at SSER after a rising

edge at SFSYNC (serial applications, S/P = 1). The de-

vice utilizes a look–ahead circuit in parallel applications

(S/P = 0), and presents data 8 clocks early as shown in

Figures 4 and 5. Converting SSER to a parallel format

requires an HC595 shift register.

022798 4/12

Share Link: