LT1306 データシートの表示（PDF） - Linear Technology

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LT1306

Synchronous, Fixed Frequency Step-Up DC/DC Converter

Linear Technology 

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OPERATIO

The LT1306 is a fixed frequency current mode PWM

regulator with integrated power transistor Q1 and syn-

chronous rectifier Q2.

In the Block Diagram, Figure 2, the PWM control circuit

is enclosed within the dashed line. It consists of the

current sense amplifier (A2), the oscillator, the compen-

sating ramp generator, the PWM comparator (A4), the

logic (X1 and X2), the power transistor driver (X4) and

the main power switch (Q1). Notice that the clock (CLK)

“blanks” Q1 conduction. The internal oscillator frequency

is 300kHz.

The pulse width of the clock determines the maximum on

duty ratio of Q1. In the LT1306 this is set to 88%. Q1 turns

on at the trailing edge of the clock pulse. To prevent

subharmonic oscillation above 50% duty ratio, a com-

pensating ramp (generated from the oscillator sawtooth)

is added to the sensed Q1 current. Q1 is turned off when

this sum exceeds the error amplifier A1 output, VC. Q1’s

absolute current limit is reached when VC’s upward

excursion is clamped internally at 1.28V.

The error amplifier output, VC, determines the peak switch

current required to regulate the output voltage. VC is a

measure of the output power. At heavy loads, the average

and the peak inductor currents are both high. VC moves to

the upper end of its operating range and the LT1306 oper-

ates in continuous conduction mode (CCM).

As load decreases, the average inductor current de-

creases. In CCM, the peak-to-peak inductor current ripple

to the first order depends only on the inductance, the

input and the output voltages. When the average inductor

current falls below 1/2 of the peak-to-peak inductor

current ripple, the converter enters discontinuous con-

duction mode (DCM). The switching frequency remains

constant except that the inductor current always returns

to zero within each switching cycle.

In both CCM and DCM, the output voltage is regulated

with negative feedback. A1 amplifies the error voltage

between the internally generated 1.24V reference and the

attenuated output voltage. The RC network from the VC

pin to ground provides the loop compensation.

Further reduction in the load moves VC towards the lower

end of its operating range. Both the peak inductor current

LT1306

and switch Q1’s on-time decrease. Hysteretic comparator

A3 determines if VC is too low for the LT1306 to operate

efficiently. As VC falls below the trip voltage VB, the output

of A3 goes high. All circuits except the error amplifier,

comparators A3 and A5, and the rectifier driver control X5,

are turned off. After the remaining energy stored in the

inductor is delivered to the output through the synchro-

nous rectifier Q2, the LT1306 stops switching. In this idle

state, the LT1306 draws only 160µA from the input. With

switching stopped and the load being powered by the

output filter capacitor, the output voltage decreases. VC

then starts to increase. Q1 does not start to switch until VC

rises above the upper trip point of A3. The LT1306 again

delivers power to the output as a current mode PWM

converter except that the switch current limit is only about

250mA due to the low value of VC. If the load is still light,

the output voltage will rise and VC will fall, causing the

converter to idle again. Power delivery therefore occurs in

bursts. The on-off cycle frequency, or burst frequency,

depends on the operating conditions, the inductance and

the output filter capacitance. The output voltage ripple in

Burst Mode operation is usually higher than either CCM or

DCM operation. Burst Mode operation increases light load

efficiency because it delivers more energy to the output

during each clock cycle than is possible with DCM

operation’s extremely low peak switch current. This al-

lows fewer switching cycles per unit time to maintain a

given output. Chip supply current therefore becomes a

small fraction of the total input current.

The synchronous rectifier is represented as NPN transis-

tor, Q2, in the Block Diagram (Figure 2). A rectifier drive

circuit, X5, supplies variable base drive to Q2 and controls

the voltage across the rectifier. The supply voltage, VCAP,

for the driver is generated locally with the bootstrap cir-

cuit, D1 and C1 (Figure 1). When Q1 is on, the bootstrap

capacitor C1 is charged from the input to the voltage

VIN – VD1(ON) – VCESAT1. The charging current flows from

the input through D1, C1 and Q1 to ground. After Q1 is

switched off, the node SW goes above VO by the rectifier

drop VCESAT2. D1 becomes back-biased and the CAP volt-

age is pushed up to VO + VCESAT2 + VIN – VD1(ON) – VCESAT1.

C1 supplies the base drive to Q2. The consumed charge is

replenished during the Q1 on interval.

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