PI6C133-03V データシートの表示（PDF） - Pericom Semiconductor
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PI6C133-03V Datasheet PDF : 15 Pages
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PI6C133-03
133 MHz Clock Generation
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The power-down controller provides a signal that is latched with
its own copy of the PCI clock.
Clock sequencing always guarantees full clock timing parameters
after the system has initially powered up, except where noted.
During power-up and power-down operations using the PWRDWN#
select pin, partial clocks are not allowed and all clock timing
parameters are met except for the following: the first clock pulse
coming out of a stopped clock condition could be slightly distorted
because of the other clock network charging requirements: it is also
understood that board routing and signal loading have a large
impact on the initial clock distortion.
VDD3V Power-Down Removal
The PI6C133-03 device meets the following requirement to
allow for a common design across multiple platforms.
To allow for multiple devices in platforms to share voltage regula-
tors, the PI6C133-03 allows the removal of power from the VDD3V
voltage pins during the following specific condition. (Leakage
currents from the VDD3V and VDD2V pins are not allowed to violate
existing powerdown# specifications.)
Going to Powerdown Mode:
1. Assert the PWRDWN# signal to the PI6C133-03.
2. Remove power from the 3.3V pins of the PI6C133-03.
3. All input pins of PI6C133-03 will be either powered down
or driven to ground.
4. VDD3 power plane will be pulled to or discharge to < 250mV.
5. The 2.5V pins will remain powered at 2.5V.
To Restore Power:
1. Apply 3.3V to the PI6C133-03.
2. Wait 200-2000ms.
3. De-assert the PWRDWN# signal.
4. Wait 1ms longer than lock time specified for the device.
5. Continue operation as normal
PI6C133-03 Clock Enable Configuration
CPUSTOP# PWRDWN# PCISTOP# CPUCLK APIC 3V66
X
0
X
LOW LOW LOW
0
1
0
LOW ON LOW
0
1
1
LOW ON LOW
1
1
0
ON
ON ON
1
1
1
ON
ON ON
PCI PCI_F REF, 48 MHz Osc VCOs
LOW LOW
LOW
OFF OFF
LOW ON
ON
ON ON
ON
ON
ON
ON ON
LOW ON
ON
ON ON
ON
ON
ON
ON ON
Notes:
1. LOW means outputs held static LOW as per latency requirement below.
2. ON means active.
3. PWRDWN# pulled LOW, impacts all outputs including REF and 48 MHz outputs.
4. All 3V66 as well as all CPU clocks should stop cleanly when CPUSTOP# is pulled LOW.
5. APIC, REF, 48 MHz signals are not controlled by the CPUSTOP# functionality and
are enabled all in all conditions except PWRDWN# = LOW.
353
PS8415
07/23/99
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