STPCC03 データシートの表示（PDF） - STMicroelectronics

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STPCC03

PC Compatible Embeded Microprocessor

STMicroelectronics 

STPC CONSUMER-S

s PCI Controller

s Fully compliant with PCI 2.1 specification.

s Integrated PCI arbitration interface. Up to 3

masters can connect directly. External PAL

allows for greater than 3 masters.

s Translation of PCI cycles to ISA bus.

s Translation of ISA master initiated cycle to

PCI.

s Support for burst read/write from PCI master.

s PCI clock is 1/3 or 1/2 Host clock .

s ISA master/slave controller

s Generates the ISA clock from either

14.318MHz oscillator clock or PCI clock

s Supports programmable extra wait state for

ISA cycles

s Supports I/O recovery time for back to back I/

O cycles.

s Fast Gate A20 and Fast reset.

s Supports the single ROM that C, D, or E.

blocks shares with F block BIOS ROM.

s Supports flash ROM.

s Supports ISA hidden refresh.

s Buffered DMA & ISA master cycles to reduce

bandwidth utilization of the PCI and Host bus.

NSP compliant.

s Integrated Peripheral Controller

s 2X8237/AT compatible 7-channel DMA

controller.

s 2X8259/AT compatible interrupt Controller.

16 interrupt inputs - ISA and PCI.

s Three 8254 compatible Timer/Counters.

s Co-processor error support logic.

s Supports external RTC.

s Local Bus interface

s Multiplxed with ISA interface.

s Low latency bus

s 22-bit address bus.

s 16-bit data bus with word steering capability.

s Programmable timing (Host clock granularity)

s 2 Programmable Flash Chip Select.

s 5 Programmable I/O Chip Select.

s Supports 32-bit Flash burst.

s 2-level hardware key protection for Flash boot

block protection.

s Supports 2 banks of 8MB flash devices with

boot block shadowed to 0x000F0000.

s IDE Interface

s Supports PIO and Bus Master IDE

s Supports up to Mode 5 Timings

s Transfer Rates to 22 MBytes/sec

s Supports up to 4 IDE devices

s Concurrent channel operation (PIO & DMA

modes) - 4 x 32-Bit Buffer FIFO per channel

s Support for PIO mode 3 & 4.

s Support for DMA mode 1 & 2.

s Support for 11.1/16.6 MB/s, I/O Channel

Ready PIO data transfers.

s Supports 13.3/16.6 MB/s DMA data transfers

s Bus Master with scatter/gather capability

s Multi-word DMA support for fast IDE drives

s Individual drive timing for all four IDE devices

s Supports both legacy & native IDE modes

s Supports hard drives larger than 528MB

s Support for CD-ROM and tape peripherals

s Backward compatibility with IDE (ATA-1).

s Power Management

s Four power saving modes: On, Doze,

Standby, Suspend.

s Programmable system activity detector

s Supports SMM.

s Supports STOPCLK.

s Supports IO trap & restart.

s Independent peripheral time-out timer to

monitor hard disk, serial & parallel ports.

s Supports RTC, interrupts and DMAs wake-up

3/51

Release B

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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