STPCC4 データシートの表示（PDF） - STMicroelectronics

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STPCC4

X86 Core PC Compatible Information Appliance System-on-Chip

STMicroelectronics 

GENERAL DESCRIPTION

1.8. CLOCK TREE

The STPC Atlas integrates many features and

generates all its clocks from a single 14MHz

oscillator. This results in multiple clock domains as

described in Figure 1-2.

The speed of the PLLs is either fixed (DEVCLK),

either programmable by strap option (HCLK)

either programmable by software (DCLK, MCLK).

When in synchronized mode, MCLK speed is fixed

to HCLKO speed and HCLKI is generated from

MCLKI.

Figure 1-2. STPC Consumer-II clock architecture

VCLK

DCLK

MCLKO

MCLKI

VIP

CRTC,Video,TV

DEVCLK

PLL

DCLK

PLL

MCLK

PLL

SDRAM controller

GE

HCLK HCLKO

PLL

ISA

CPU

x1 HCLKI

x2

IPC

South Bridge

North Bridge

Host

Local Bus

1/2

1/3

1/2 1/4

DEVCLK

(24MHz)

XTALO

XTALI

14.31818 MHz

OSC14M ISACLK

(14MHz)

PCICLKI

HCLK

PCICLKO

Release 1.5 - January 29, 2002

9/93

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