STPCI2 データシートの表示（PDF） - STMicroelectronics

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STPCI2

X86 CORE PC COMPATIBLE SYSTEM-ON-CHIP FOR TERMINALS

STMicroelectronics 

STPC® ATLAS

DESCRIPTION

8MB for PCI/ISA busses.

The STPC Atlas integrates a standard 5th

generation x86 core along with a powerful UMA

graphics/video chipset, support logic including

PCI, ISA, Local Bus, USB, EIDE controllers and

combines them with standard I/O interfaces to

provide a single PC compatible subsystem on a

single device, suitable for all kinds of terminal and

industrial appliances.

■ 32-bit access, Autoprecharge & Power-down

are not supported.

■ Enhanced 2D Graphics Controller

■ Supports pixel depths of 8, 16, 24 and 32 bit.

■ Full BitBLT implementation for all 256 raster

operations defined for Windows.

■ Supports 4 transparent BLT modes - Bitmap

Transparency, Pattern Transparency, Source

■ X86 Processor core

Transparency and Destination Transparency.

■ Fully static 32-bit 5-stage pipeline, x86

■ Hardware clipping

processor fully PC compatible.

■ Fast line draw engine with anti-aliasing.

■ Can access up to 4GB of external memory.

■ Supports 4-bit alpha blended font for anti-

■ 8Kbyte unified instruction and data cache

aliased text display.

with write back and write through capability.

■ Parallel processing integral floating point unit,

) with automatic power down.

t(s ■ Runs up to 133 MHz (X2).

c ■ Fully static design for dynamic clock control.

u ■ Low power and system management modes.

rod ■ Optimized design for 2.5V operation.

P ■ SDRAM Controller

te ■ 64-bit data bus.

le ■ Up to 90MHz SDRAM clock speed.

o ■ Integrated system memory, graphic frame

s memory and video frame memory.

b ■ Supports 8MB up to 128 MB system memory.

O ■ Supports 16-Mbit, 64-Mbit and 128-Mbit

) - SDRAMs.

t(s ■ Supports 8, 16, 32, 64, and 128 MB DIMMs.

■ Supports buffered, non buffered, and

uc registered DIMMs

d ■ 4-line write buffers for CPU to DRAM and PCI

ro to DRAM cycles.

P ■ 4-line read prefetch buffers for PCI masters.

te ■ Programmable latency

■ Programmable timing for SDRAM

le parameters.

so ■ Supports -8, -10, -12, -13, -15 memory parts

Ob■ Supports memory hole between 1MB and

■ Complete double buffered registers for

pipelined operation.

■ 64-bit wide pipelined architecture running at

90 MHz. Hardware clipping

■ CRT Controller

■ Integrated 135MHz triple RAMDAC allowing

for 1280 x 1024 x 75Hz display.

■ 8-, 16-, 24-bit pixels.

■ Interlaced or non-interlaced output.

■ Video Input port

■ Accepts video inputs in CCIR 601/656 mode.

■ Optional 2:1 decimator

■ Stores captured video in off setting area of

the onboard frame buffer.

■ HSYNC and B/T generation or lock onto

external video timing source.

■ Video Pipeline

■ Two-tap interpolative horizontal filter.

■ Two-tap interpolative vertical filter.

■ Color space conversion (RGB to YUV and

YUV to RGB).

■ Programmable window size.

■ Chroma and color keying for integrated video

overlay.

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