PI74SSTV16859(2000) データシートの表示（PDF） - Pericom Semiconductor
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PI74SSTV16859 Datasheet PDF : 7 Pages
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ADVANCE INFORMATION
PI74SSTV16859
13-Bit to 26-Bit Registered Buffer
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Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted)
VDD = 2.5V ±0.2V
Min.
Max.
fclock
Clock frequency
200
tW
Pulse Duration, CK, CK high or low
2.5
tact
Differential Inputs active time, data inputs must be low after RESET high.
22
tinact
Differential Inputs inactive time, data and clock inputs must be held at valid
levels (not floating) after RESET Low.
Setup time, fast slew rate(5,7)
0.75
tsu
Setup time, slow slew rate(6,7)
Data before CK↑, CK↓
0.9
Hold time, fast slew rate(5,7)
0.75
th
Hold time, slow slew rate(6,7)
Data after CK↑, CK↓
0.9
Units
MHz
ns
Notes:
5. For data signal input slew rate ≥1V/ns.
6. For data signal input slew rate ≥0.5V/ns and <1V/ns.
7. CLK, CLK signals input slew rates are ≥1V/ns.
This parameter is not necessarily production tested.
Switching characteristics
(Over recommended operating free-air temperature range, unless otherwise noted.)
(See test circuits and switching waveforms).
Parameter
From
(Input)
To
(Output)
VDD = 2.5V ±0.2V
Min. Typ. Max.
Units
fmax
170
MHz
tpd
CLK, CLK
Q
1.1
tphl
RESET
Q
2.8
ns
5.0
5
PXXXX 07/27/00
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