SAA5355 データシートの表示（PDF） - Philips Electronics

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SAA5355

Single-chip colour CRT controller (FTFROM)

Philips Electronics 

Philips Semiconductors

Single-chip colour CRT controller

(FTFROM)

Product specification

SAA5355

Scroll map

The scroll map uses a 26-byte area of on-chip RAM and functions in association with the timing chain. It maps the scan

row on to the fetched memory row so allowing the stored page to be displayed in any row order. For each row, a 1-byte

pointer to the display memory row is stored in the scroll map. This allows scrolling without the need for data transfer to,

or from, side storage.

Additional control bits are stored, allowing 1 to 25 rows to be displayed at any location on the screen.

Colour map and digital-to-analogue converters

The colour map RAM contains thirty-two 12-bit words that are loaded by the microprocessor and read out in three 4-bit

groups at pixel rate. Each group is fed to a non-linear (gamma-corrected) D-A converter. The resulting R, G and B outputs

are low-impedance with peak-to-peak amplitudes controlled by the reference voltage applied at pin 21.

Cursor

The cursor is available in the stack mode. Its position, character code, character table, foreground colour, background

colour, lining and flash attributes are all software programmable via internal register bits.

NON-VIDEOTEX APPLICATIONS

For non-Videotex applications, the device will also support the following operating modes:

Explicit fill mode. An alternative 40 character/rows mode which does not use the memory compression technique of

stack coding. More display memory is required but there are no limitations on the number of display attribute changes

per row.

80 characters/rows mode. When operating with 80 characters per row, the available display attributes are eight

foreground colours, eight (potentially different) background colours (including transparent) as well as underline and blink.

Full field DRCS mode. This mode is not mutually exclusive to the explicit fill and 80 characters/rows modes but rather

the available DRCS memory is expanded so that the whole screen can be covered, thus enabling a ‘bit map’. All

ROM-based characters and all display attributes remain available.

MICROPROCESSOR and RAM BUS INTERFACE

Three types of data transfer take place at the bus interface:

• FTFROM fetches data from the display memory

• The microprocessor reads from, or writes to, FTFROM’s internal register map

• The microprocessor accesses the display memory

FTFROM access to display memory (Figs 17 and 18)

FTFROM accesses the external display memory via a 16-bit multiplexed address and data bus with a cycle time of

496,5 ns (F6 = 6,041957 MHz). The address strobe (AS) signal from FTFROM flags the bus cycle and writes the address

into octal latches (74LS373). The display data is stored in bytes of upper (most-significant) and lower (least-significant)

display information and is always fetched in pairs of bytes (upper + lower = 16 bits). The upper and lower display RAM

sections are enabled simultaneously by the upper and lower data strobes (respectively UDS and LDS) which are always

asserted together to fetch a 16-bit word. The read/write control R/W is included although FTFROM only reads from the

display memory.

March 1986

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