M37640E8 データシートの表示（PDF） - MITSUBISHI ELECTRIC
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M37640E8 Datasheet PDF : 172 Pages
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Mitsubishi Microcomputer
7600 Series
M37640E8-XXXF Preliminary Specification
MSB
7
AME RTS_SEL CTS_SEL TIS
RIN
TIN
REN
TEN
LSB Address: 003316,003B16
0 Access: R/W
TEN
REN
TIN
RIN
TIS
CTS_SEL
RTS_SEL
AME
Transmission Enable Bit (bit 0)
0: Disable the transmit process
Reset: 0016
1: Enables the transmit process. If the transmit process is disabled (TEN cleared)
during transmission, the transmit will not stop until completed.
Receive Enable Bit (bit 1)
0: Disable the receive process
1: Enables the receive process. If the receive process is disabled (REN cleared)
during reception, the receive will not stop until completed.
Transmission Initialization Bit (bit 2)
0: No action.
1: Resets the UART transmit status register bits as well as stopping the transmission
operation. The TEN bit must be set and the transmit buffer reloaded in order to transmit
again. The TIN is automatically reset one cycle after TIN is set.
Receive Initialization Bit (bit 3)
0: No action.
1: Clears the UART receive status flags and the REN bit. If RIN is set during receive in
progress, receive operation is aborted. The RIN bit is automatically reset one cycle
after RIN is set.
Transmit Interrupt Source Selection Bit (bit 4)
0: Transmit interrupt occurs when the Transmit Buffer Empty flag is set.
1: Transmit interrupt occurs when the Transmit Complete flag is set.
Clear-to-Send (CTS) Enable Bit (bit 5)
0: CTS function is disabled, P86 (or P82) is used as GPIO pin.
1: CTS function is enabled, P86 (or P82) is used as CTS input.
Request-to-Send (RTS) Enable Bit (bit 6)
0: RTS function is disabled, P87 (or P83) is used as GPIO pin.
1: RTS function is enabled, P87 (or P83) is used as RTS output.
UART Address Mode Enable Bit (bit 7)
0: Address Mode disabled.
1: Address Mode enabled.
Figure 5-22. UxCON Register
MSB
7
RTS3
Bits 0-3
RTS3:0
RTS2
RTS1
RTS0
Reserved
Reserved
Reserved
Reserved LSB
0
Reserved (Read/Write “0”)
RTS Assertion Delay Count 3:0 (bits 7,6,5,4)
0000:
No delay, RTS asserts immediately after receive operation completes.
0001:
RTS asserts 8 bit-times after receive operation completes.
0010:
RTS asserts 16 bit-times after receive operation completes.
0011:
RTS asserts 24 bit-times after receive operation completes.
.
.
.
1000:
RTS asserts 64 bit-times after receive operation completes.
.
.
.
1110:
RTS asserts 112 bit-times after receive operation completes.
1111:
RTS asserts 120 bit-times after receive operation completes.
Address: 003616, 003E16
Access: R/W
Reset: 8016
Figure 5-23. UxRTSC Register
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