A61L6316S-10 データシートの表示（PDF） - AMIC Technology

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A61L6316S-10

64K X 16 BIT HIGH SPEED CMOS SRAM

AMIC Technology 

AC Test Conditions

Input Pulse Levels

Input Rise And Fall Time

Input and Output Timing Reference Levels

Output Load

0V to 3.0V

3 ns

1.5 V

See Figures 1 and 2

A61L6316 Series

OUTPUT

ZO=50Ω

RL=50Ω

VT=1.5V

Figure 1. Output Load

Data Retention Characteristics (TA = 0°C to 70°C)

Symbol

Parameter

Min.

VDR VCC for Data Retention

2

ICCDR Data Retention Current

-

Chip Disable to Data Retention

tCDR

Time

tR

Operation Recovery Time

tRC = Read Cycle Time

0

TRC*

+3.3V

317Ω

I/O

351Ω

5pF*

* Including scope and jig.

Figure 2. Output Load for tCLZ, tOLZ,

tCHZ, tOHZ, tWHZ, and tOW

Max.

3.6

5

-

-

Unit

Conditions

V

CE ≥ VCC - 0.2V

VCC = 2.0V

mA

CE ≥ VCC - 0.2V

VIN ≥ VCC - 0.2V or

VIN ≤ 0.2V

ns

See Retention Waveform

ms

(May, 2001, Version 1.0)

11

AMIC Technology, Inc.

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