RS8234 データシートの表示（PDF） - Conexant Systems
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RS8234 Datasheet PDF : 8 Pages
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Multi-Queue Reassembly Processing
• 32 reassembly queues
• 64K VCCs maximum **
• AAL5 and AAL3/4 CPCS checking
• AAL0
– PTI termination
– Cell count termination
• Early packet discard, based on:
– Receive buffer underflow
– Receive status overflow
– CLP with priority threshold
– AAL5 max PDU length
– Rx FIFO full
– Frame Relay DE with priority threshold
– LECID filtering for echo suppression
– Per-VCC firewalls
• Dynamic channel lookup (NNI or UNI addressing)
– Supports full address space
– Deterministic
– Flexible VCI count per VPI
– Optimized for signaling address assignment
• Message and streaming status modes
• Raw cell mode (52 octet)
• 200 Mbps half duplex
• 155 Mbps full duplex (with 2-cell PDUs)
• Distributed host or SAR shared
memory reassembly
• 8 programmable reassembly hardware
time-outs (assignable per VCC )
• Global max PDU length for AAL5
• Per-VCC buffer firewall (memory usage limit)
• Simultaneous reassembly and segmentation
• Idle cell filtering
• 32K duplex VCCs
High-Performance Host Architecture
with Buffer Isolation
• Write-only control and status
• Read multiple command for data transfer
• Up to 32 host clients control and status queues
• Physical or logical clients
– Enables peer-to-peer architecture
• Descriptor-based buffer chaining
• Scatter/gather DMA
• Endian neutral
• Non-word (byte) aligned host buffer addresses
• Automatically detects presence of Tx data
or Rx free buffers
• Virtual FIFOs (PCI bursts treated as single address)
• Hardware indication of BOM
• Allows isolation of system resources
• Status queue interrupt delay
Designer Toolkit
• Evaluation module (RS8234EVM)
• Reference schematics
• Hardware Programming Interface –
RS8234HPI reference source code (C)
Generous Implementation
of OAM-PM Protocols
• Detection of all F4/F5 OAM flows
• Internal PM monitoring and generation for
up to 128 VCCs
• Optional global OAM Rx/Tx queues
• In-line OAM insertion and generation
Standards-Based I/O
• 33 MHz PCI 2.1
• Serial EEPROM to store PCI
configuration information
• PHY Interfaces
– UTOPIA master (Level 1)
– UTOPIA slave (Level 1)
• Flexible SAR-shared memory
architecture
• Optional local control interface
• Boundary scan for board-level testing
• Source loopback, for diagnostics
• Glueless connection to Conexant’s
RS8250 ATM PHY device
Electrical/Mechanical
• 388-pin BGA package
• 3.3V power supply
• 5V tolerant I/O pads
• 5V - 3.3V PCI pads
• Low power 1.0 W (typical) at full rate
• Industrial temperature range
• TTL level inputs
• CMOS level outputs
Standards Compliance
• UNI/NNI 3.1
• T.M. 4.1
• Bellcore GR-1248
• ATM Forum B-ICI V 2.0
• I.363
• I.610 /GR-1248
• AToM MIB (RFC1695)
• ILMI MIB
• ANSI T1.635
• GFC per I.361
• SNMP
• I2C Protocol
• PCI Revision 2.1
• IEEE 1149.1-1990
• IEEE 1149.1 supplement B, 1994
Statistics and Counters
• Global register counter of # of
cells transmitted
• Global register counter of # of
cells received on active channels
• Global register counter of # of cells
received on inactive channels
• Global register counter of # of AAL5
CPCS-PDUs discarded due to
per-channel firewall, etc
• RSM per VCC service discard counters
(Frame Relay and LANE)
• 1 programmable interval timer
(32 bits with interrupt)
• Per-VCC AAL3/4 MIB counters:
– # cells with CRC10 errors
– # cells with MID errors
– # cells with LI errors
– # cells with SN errors
– # cells with BOM or SSM errors
– # cells with EOM errors
** Depends on local memory size and device
configuration; 32K VCCs typically.
What is ATM?
Asynchronous Transfer Mode (ATM) has emerged as the
primary networking technology for next-generation, multi-
service communication networks. ATM-enabled services
benefit the Internet as well as emerging applications in
science, telemedicine and distance learning. Just as the
Internet revolutionized worldwide communications, ATM
brings new meaning to high-speed networking.
ATM, which uses a fixed-size packet, or cell, is a transport
protocol capable of providing a homogeneous network for
all traffic types, whether the application is to carry conven-
tional telephony, video entertainment, or data traffic over
LANs, MANs or WANs.
The ITU-T and ANSI selected ATM for Broadband-ISDN.
SONET/SDH, as specified by the ITU, is intended as the
primary transport mechanism for ATM cells in WAN
applications. ATM also plays a key role in next-generation
consumer applications for high-speed Internet access and
wireless access. The ADSL Forum and the Universal ADSL
Working Group chose ATM as the network layer protocol
for G.lite and G.DMT ADSL.
ATM physical-layer (ATM-PHY) IC devices adapt ATM cells
to and from transmission rates ranging from 1.544 Mbps to
2.4 Gbps, via a standard system interface called UTOPIA.
ATM-PHY devices perform ATM cell functions (transmis-
sion convergence) such as cell scrambling/descrambling,
cell delineation (HEC), cell header processing, and cell-rate
decoupling as well as rate-specific functions for frame gen-
eration/recovery, frame adaptation and clock/data recovery.
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