STV1602A データシートの表示（PDF） - STMicroelectronics
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STV1602A Datasheet PDF : 22 Pages
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STV1602A
EQUALIZER (VEE = -5V, TA = 25oC unless otherwise specified)
Symbol
VMAX
GMAX
CIN
RIN
Parameter
Equalizer Max. Input Voltage
Equalizer Max. Gain
Input Capacity
Input Resistance
Test Conditions
Pins AIX, AIY
Pins AIX, freq = 100MHz
Pins AIX, freq = 100MHz
Test Circuit Min.
Figure 3 0.88
Typ.
30
Max.
Unit
Vp-p
dB
pF
Ω
Figure 1 : tr, tf, tc, td Definition
80%
Dn
tc
t c /2
tc /2
20%
PCK
50%
tr
tf
td
tw
SYN pin guaranteed operation range.
SYNC pin and serial to parallel conversion operate
normally within the frequency and ambient tem-
perature ranges according to the following consid-
erations.
Reclocked output.
STV1602A may be used as a repeater. The re-
clocked output, providing characteristics almost
identical to the serial output of STV1601A is avail-
able from SX (Pin 4) and SY (Pin 3).
When the reclocked output is used, it is recom-
mended not to use simultaneously use the parallel
outputs (data and clock) in order to avoid possible
logic errors caused by an excessively high tem-
perature which may result from additional power
dissipation created by the reclocked output circuit
under certain environnmental conditions.
If, for the sake of a design convenience, both
reclocked and parallel outputs are to be used, the
ambient temperature has to be kept as low as
possible or, at least, the airflow around STV1602A
must be carefully considered. In addition, it is rec-
ommended to put 220Ω resistors on all parallel
outputs including the clock as shown in Figure 2.
This reduces the magnitude of the spike current
resulting from the parallel output circuit inside the
chip and helps reduce the probability of logic errors
at high temperature.
Power saving in repeater mode
Since the parallell output is not always required for
a reclocked repeater, the chip has been designed
such that the uncessary parallel logic circuit can be
disabled by disconnecting Pin 8, one of VEEs, from
the power supply. With this arrangement the power
dissipation is reducible to about 45 percent of that
of the fully functional mode.
In practice, a test switch should be provided so that
some parallel signals may be available during ad-
justment procedures as shown in Figure 2.
Figure 2 : A Suggested Parallel Clock / Data
Output Circuit
EVR 21
1kΩ
PCK 19
1kΩ
D0 18
1kΩ
STV1602A
V EE D9 9
8
1kΩ
Power save SW
220Ω
220Ω
220Ω
ECL line drivers or
ECL/TTL translators
0.1µF
V EE (-5V)
9/22
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