![](/html/Yamaha/1187/page6.png)
M,S,FA bit SYNCHW/B1, B2 bit
Layer 3 interface block
Clock
generator
Internal block
DPLL
Multi-
frame
control
Frame
synchro-
nization
CH-A HDLC
frame disassembly
CH-A HDLC
frame assembly
CH-A HDLC
frame disassembly
CH-A HDLC
frame assembly
Buffer
Buffer
Buffer
Buffer
Bch interface
B
B channel control block
Bch
DMAC
Internal
controller
Register
HRD
LRD
HTD
LTD
Frame disassembly
D HDLC frame
disassembly
Layer 1
S
control block
Q
Frame assembly
Priority, collision
D, E control
BD
HDLC frame assembly
Buffer
Buffer
Buffer
FA bit
Layer 2 control block
Dch
DMAC
Internal bus