A(12:0)
DQ(7:0)
Assumptions:
1 . E1 and G < V IL (max)
2 . E2 and W > VIH (min)
A(12:0)
E2
E1
tETQV
DQ(7:0)
Assumptions:
1. G < VIL (max) and W > VIH (min)
tAVAV
tA X Q X
tAVQV
Figure 3a. SRAM Read Cycle 1: Address Access
tETQX
tEFQZ
DATA VALID
Figure 3b. SRAM Read Cycle 2: Chip Enable Access
A(12:0)
G
DQ(7:0)
Assumptions:
1 . E1 < VIL (max)
2 . E2 and W > VIH (min)
tGLQX
tGLQV
DATA VALID
tG H Q Z
Figure 3c. SRAM Read Cycle 3: Output Enable Access
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