CD4502BMS データシートの表示（PDF） - Intersil

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CD4502BMS

CMOS Strobed Hex Inverter/Buffer

Intersil 

CD4502BMS

December 1992

CMOS Strobed Hex Inverter/Buffer

Features

Pinout

• High Voltage Type (20V Rating)

• 2 TTL Load Output Drive Capability

CD4502BMS

TOP VIEW

• 3 State Outputs

• Common Output Disable Control

• Inhibit Control

• 100% Tested for Quiescent Current at 20V

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current of 1µA at 18V Over Full Pack-

age Temperature Range; 100nA at 18V and +25oC

• Noise Margin (Over Full Package/Temperature Range)

- 1V at VDD = 5V

- 2V at VDD = 10V

- 2.5V at VDD = 15V

D3 1

Q3 2

D1 3

3 STATE

OUTPUT DISABLE

4

Q1 5

D2 6

Q2 7

VSS 8

16 VDD

15 D6

14 Q6

13 D5

12 INHIBIT

11 Q5

10 D4

9 Q4

• Meets All Requirements of JEDEC Tentative Standard

No. 13B, “Standard Specifications for Description of

‘B’ Series CMOS Devices”

Applications

Functional Diagram

• 3 State Hex Inverter for Interfacing ICs with Data

Buses

• COS/MOS to TTL Hex Buffer

Description

CD4502BMS consists of six inverter/buffers with 3 state

outputs. A logic “1” on the OUTPUT DISABLE input

produces a high impedance state in all six outputs. This

feature permits common busing of the outputs, thus

simplifying system design. A Logic “1” on the INHIBIT input

switches all six outputs to logic “0” if the OUTPUT DISABLE

input is a logic “0”. This device is capable of driving two

standard TTL loads, which is equivalent to six times the

JEDEC “B” series IOL standard.

3 STATE 4

OUTPUT DISABLE

INHIBIT 12

D1 3

D2 6

D3 1

D4 10

D5 13

D6 15

5 Q1

7 Q2

2 Q3

9 Q4

11 Q5

14 Q6

The CD4502BMS is supplied in these 16-lead outline packages:

Braze Seal DIP

Frit Seal DIP

Ceramic Flatpack

H4T

H1F

H6W

VDD = 16

VSS = 8

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

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File Number 3334

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