SY100S302 データシートの表示（PDF） - Micrel
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SY100S302 Datasheet PDF : 4 Pages
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Micrel, Inc.
QUINT 2-INPUT
OR/NOR GATE
SY100S302
SY100S302
FEATURES
DESCRIPTION
s Max. propagation delay of 700ps
s IEE min. of –45mA
s Industry standard 100K ECL levels
s Extended supply voltage option:
VEE = –4.2V to –5.5V
s Voltage and temperature compensation for
improved noise immunity
s Internal 75kΩ input pull-down resistors
s 50% faster than Fairchild 300K
s Function and pinout compatible with Fairchild F100K
s Available in 28-pin PLCC package
The SY100S302 offers five 2-input OR/NOR gates
designed for use in high-performance ECL systems. The
five gates are controlled by a common Enable signal. All
inputs have 75kΩ pull-down resistors and all outputs are
buffered.
BLOCK DIAGRAM
D1a
Oa
D2a
Oa
D1b
Ob
D2b
Ob
D1c
Oc
D2c
Oc
D1d
Od
D2d
Od
D1e
Oe
D2e
Oe
E
PIN NAMES
Pin
Dna – Dne
E
Oa – Oe
Oa – Oe
VEES
VCCA
Function
Data Inputs (n-1...5)
Enable Input
Data Outputs
Complementary Data Outputs
VEE Substrate
VCCO for ECL Outputs
M9999-042307
hbwhelp@micrel.com or (408) 955-1690
1
Rev.: I
Amendment: /0
Issue Date: April 2007
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