QL80FC-PB456I データシートの表示（PDF） - QuickLogic Corporation

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QL80FC-PB456I

QuickLogic QL80FC Programmable Fibre Channel ENDEC

QuickLogic Corporation 

QL80FC - QuickFCTM

TRANSMIT DATA PATH

Transmit Data Path

When the transmit data path is in standard operation

(TxRawEn not asserted) the chip will latch an un-

encoded, Fibre Channel, 32-bit word on inputs

TxData[31:0]. This data then passes on to the 8b/

10b encoder, which creates a 40-bit encoded Fibre

Channel word. The encoder will encode the most sig-

nificant character as a command character if the

TxKChar input line is asserted. This word is regis-

tered and passed to the SERDES in 20-bit chunks (10

bit chunks if 10 bit mode is enabled) on the TxOut

signal lines.

Asserting the TxCrcEn signal enables the CRC Gen-

eration block. This block will automatically detect the

SOF ordered set and begin CRC generation using the

ANSI specified CRC polynomial. It will continue until

an EOF or any other FC ordered set is encountered

(unless TxIFIdleEn is asserted, then the IDLE ordered

set will be ignored by the CRC generator). It then

inserts the CRC value into the data path for transmis-

sion to the SERDES.

The TxRawEn signal enables the raw transmit data

path when asserted. In this mode, the 8 bits of TxR-

Data is concatenated onto the 32 bits of the TxData

signal to create a 40-bit wide data path. The CRC

generation and 8b/10b encoder blocks are bypassed

and the “raw” data latched at the inputs is passed

directly to the output registers that drive the SER-

DES. This mode is useful for testing the error han-

dling capabilities of the serial link by providing the

systems designer a way to intentionally introduce

errors into the serial bit stream.

The TxIFIdleEn (Intra-Frame Idle Enable) input

enables the use of Fibre Channel IDLE words within

a Frame. When this signal is asserted, IDLE words

present within a data frame will not affect the value

generated by the CRC block. This feature is useful in

custom FC designs where it is desired to suspend the

transmission of a frame for a period of time and then

resume later.

The use of external FIFOs is optional. There is

enough RAM on the ENDEC chip to be configured

into two 352 x 36 FIFOs. If FIFOs of this size are all

that is required, external FIFOs would not be needed.

Synchronous read and writes directly from the system

bus without a FIFO is also possible.

Two clock signals are supplied to the customizable

logic on high speed, low skew clock networks:

TxClk125 and TxClk63. TxClk125 is a clock run-

ning at a maximum speed of 125 MHz, and repre-

sents the “full speed” of the Oscillator being used to

clock the transmit data path. The input that drives

this signal is also used to clock the SERDES chip.

The TxClk63 clock signal operates at half the speed

of the TxClk125 clock. You will most likely want to

use the TxClk63 signal to clock your FIFOs and cus-

tomizable logic. Of course, these signals can be

routed off-chip through the customizable I/O.

The Async_rst pin accepts an asynchronous, active

high reset signal. Circuitry takes this signal and syn-

chronizes it with the TxClk63 clock. This synchro-

nous reset signal, TxRst, is used to set or clear flip-

flops in the transmit data path. It is made available to

the user programmable logic for the same purpose

on a high speed, low skew network

The Clk_rst input stops the TxClk63 clock when this

signal is asserted. This signal was added primarily to

facilitate simulation. Clk_rst may be permanently

grounded in hardware.

4

4Preliminary

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