QL80FC-PQ208C データシートの表示（PDF） - QuickLogic Corporation

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QL80FC-PQ208C

QuickLogic QL80FC Programmable Fibre Channel ENDEC

QuickLogic Corporation 

QL80FC - QuickFCTM

System

Bus

Micro-Processor

Or

System Bus

Interface

(Optional)

Transmit

FIFO

(Optional)

Receive

FIFO

QL80FC Programmable ENDEC Chip

User Customizable

Logic

FIFO Control

Internal

Transmit

FIFO

Internal

Receive

FIFO

Bridge Logic

For Data Path

Embedded

Fibre Channel

ENDEC

Transmit/

Receive

SERDES

2.5 Gb/s Serial

Data Over

Copper or

Optical Cable

FIGURE 1. System Level Diagram

GENERAL DESCRIPTION

General Description

The QL80FC device in the QuickLogic QuickFC ESP

(Embedded Standard Product) family provides a com-

pletely integrated configurable Fibre Channel

Encoder/Decoder interface solution combined with

customizable logic. This device provides a means to

receive and transmit high-speed serial data and

implement a Fibre Channel Link interface or any

proprietary high-speed serial link.

The chip is divided into two main portions, an

embedded design and a customizable design. The

embedded design contains the built in functionality of

Fibre Channel's FC-1 and FC-2 layers, which the sys-

tem designer uses as a standard product. This portion

can not be modified. As such, all functionality and

timing requirements have been verified in hardware

and are guaranteed.

The customizable portion consists of user customiz-

able system gates, and interfaces directly to the

embedded portion of the chip. These gates may be

programmed to implement glue logic to other bus

standards such as PCI or SCSI. They can also be pro-

grammed with Fibre Channel Upper Layer Protocols.

Of course, the designer may choose to modify Upper

Layer Protocols for customization. In this way, the

2

QuickLogic QL80FC provides the embedded systems

designer with an easy to use and cost effective solu-

tion for embedded serial applications.

Fibre Channel Application

FIBRE CHANNEL APPLICATIONS

The QL80FC ENDEC is a high performance

encoder/decoder designed for use in conjunction

with Gb/s SERDES transmitter/receiver chips. These

chips, when combined with internal FIFO buffer

memory, can be used to build a complete serial link.

Optional, external FIFOs can be used in place of the

available internal FIFOs to extend buffering to sizes

beyond 352 words.

The embedded ENDEC is a full duplex design with an

encoder section for transmission and a decoder sec-

tion for reception. The transmitter/encoder section

accepts a 4-byte user data word, encodes each byte

into a 10-bit transmission character and outputs

transmission characters to the SERDES transmitter.

This equals two 10-bit characters per clock (one 10-

bit character per clock in 10-bit mode). The receiver/

decoder section accepts two 10-bit transmission char-

2Preliminary

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