DS21Q41BTN データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated
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DS21Q41BTN Datasheet PDF : 55 Pages
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DS21Q41B
DS21Q41B FRAMER DECODE Table 1–6
FS1
FS0
0
0
0
1
1
0
1
1
FRAMER ACCESSED
#0
#1
#2
#3
2.0 PARALLEL PORT
The DS21Q41B is controlled via either a non–mutli-
plexed (MUX=0) or multiplexed (MUX=1) by an external
microcontroller or microprocessor. The DS21Q41B can
operate with either Intel or Motorola bus timing configu-
rations. If the BTS pin is tied low, Intel timing will be
selected; if tied high, Motorola timing will be selected.
All Motorola bus signals are listed in parenthesis (). See
the timing diagrams in the A.C. Electrical Characterist-
ics for more details.
3.0 CONTROL REGISTERS
The operation of each framer within the DS21Q41B is
configured via a set of seven registers. Typically, the
control registers are only accessed when the system is
first powered up. Once the DS21Q41B has been initial-
ized, the control registers will only need to be accessed
when there is a change in the system configuration.
There are two Receive Control Registers (RCR1 and
RCR2), two Transmit Control Registers (TCR1 and
TCR2), and three Common Control Registers (CCR1,
CCR2, and CCR3).
RCR1: RECEIVE CONTROL REGISTER 1 (Address=2B Hex)
(MSB)
LCVCRF
ARC
OOF1
OOF2
SYNCC
CYNCT
SYNCE
(LSB)
RESYNC
SYMBOL
LCVCRF
POSITION
RCR1.7
ARC
RCR1.6
OOF1
RCR1.5
OOF2
RCR1.4
SYNCC
RCR1.3
SYNCT
RCR1.2
NAME AND DESCRIPTION
Line Code Violation Count Register Function Select.
0=do not count excessive zeros
1=count excessive zeros
Auto Resync Criteria.
0=Resync on OOF or RCL event
1=Resync on OOF only
Out Of Frame Select 1.
0=2/4 frame bits in error
1=2/5 frame bits in error
Out Of Frame Select 2.
0=follow RCR1.5
1=2/6 frame bits in error
Sync Criteria. In D4 Framing Mode.
0=search for Ft pattern, then search for Fs pattern
1=cross couple Ft and Fs pattern
In ESF Framing Mode.
0=search for FPS pattern only
1=search for FPS and verify with CRC6
Sync Time.
0=qualify 10 bits
1=qualify 24 bits
021997 11/55
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