SP486 データシートの表示（PDF） - Signal Processing Technologies
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コンポーネント説明
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SP486 Datasheet PDF : 7 Pages
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PINOUT — SP486
DI1 1
1
DO1A 2
DO1B 3
EN 4
DO2B 5
DO2A 6
2
DI2 7
GND 8
SP486 16 VCC
15 DI4
4
14 DO4A
13 DO4B
12 EN
11 DO3B
10 DO3A
3
9 DI3
SP486 PINOUT
Pin 1 — DI1 — Driver 1 Input — If Driver 1 output is
enabled, logic 0 on DI1 forces driver output DO1A low
and DO1B high. A logic 1 on DI1 with Driver 1 output
enabled forces driver DO A high and DO B low.
1
1
Pin 2 — DO A — Driver 1 output A.
1
Pin 3 — DO1B — Driver 1 output B.
Pin 4 — EN — Driver Output Enable. Please refer to
SP486 Truth Table (1).
Pin 5 — DO2B — Driver 2 output B.
Pin 6 — DO2A — Driver 2 output A.
Pin 7 — DI2 — Driver 2 Input — If Driver 2 output is
enabled, logic 0 on DI2 forces driver output DO2A low
andDO Bhigh.Alogic1onDI withDriver2output
2
2
enabled forces driver DO A high and DO B low.
2
2
S1
OUTPUT
500 ohms
VCC
UNDER TEST CL
S2
Figure 3. Driver Timing Test Load
Pin 8 — GND — Digital Ground.
Pin 9 — DI3 — Driver 3 Input — If Driver 3 output is
enabled, logic 0 on DI3 forces driver output DO3A low
and DO3B high. A logic 1 on DI3 with Driver 3 output
enabled forces driver DO3A high and DO3B low.
Pin 10 — DO3A — Driver 3 output A.
Pin 11 — DO B — Driver 3 output B.
3
Pin 12 — EN — Driver Output Disable. Please refer
to SP486 Truth Table (1).
Pin 13 — DO4B — Driver 4 output B.
Pin 14 — DO4A — Driver 4 output A.
Pin 15 — DI4 — Driver 4 Input — If Driver 4 output
is enabled, logic 0 on DI4 forces driver output DO4A
low and DO B high. A logic 1 on DI with Driver 3
4
4
output enabled forces driver DO A high and DO B
4
4
low.
A
VDO
B
R
R VOC
Figure 1. Driver DC Test Load
EN
CL1
A
DI DRIVER
RDIFF
B
CL2
EN
Figure 2. Driver Timing Test
SP486/487
Quad RS-485/RS-422 Line Drivers
3
© Copyright 2000 Sipex Corporation
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