EN
RIN+
R IN-
VDD
2K
20pf
2K
Figure 6. Receiver Three-State Delay Test Circuit or Equivalent Circuit
EN when EN = VDD
EN when EN = VSS
Output when
VID = -100mV
Output when
VID = +100mV
1.25V
1.25V
tPLZ
tPHZ
1.25V
1.25V
0.5V
0.5V
tPZL
tPZH
VDD
0V
VDD
0V
50%
50%
VDD
VO L
VOH
VSS
Figure 7. Receiver Three-State Delay Waveform
8