U634H256 データシートの表示（PDF） - Zentrum Mikroelektronik Dresden AG

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U634H256

PowerStore 32K x 8 nvSRAM

Zentrum Mikroelektronik Dresden AG 

U634H256

Software Controlled STORE/RECALL Cyclet, u, v, w (E = HIGH after STORE initiation)

Ai

E

DQi

Output

tcR (29)

ADDRESS 1

tw(E)SR (34)

tsu(A)SR (33)

High Impedance

(35)

th(A)SR

VALID

tcR (29)

ADDRESS 6

tw(E)SR (34) th(A)SR (35)

(33)

tsu(A)SR

tdis(E) (5)

td(E)S (31) td(E)R (32)

VALID

tdis(E)SR (30)

Software Controlled STORE/RECALL Cyclet, u, v, w (E = LOW after STORE initiation)

Ai

E

DQi

Output

tcR (29)

ADDRESS 1

tw(E)SR (34)

tsu(A)SR (33)

th(A)SR (35)

High Impedance VALID

ADDRESS 6

th(A)SR (35)

(33)

tsu(A)SR

td(E)S (31)

VALID

tdis(E)SR (30)

td(E)R (32)

u: If the chip enable pulse width is less then ta(E) (see READ cycle) but greater than or equal to tw(E)SR, then the data may not be valid at

the end of the low pulse, however the STORE or RECALL will still be initiated.

v: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW

throughout. Addresses 1 through 6 are found in the mode selection table. Address 6 determines whether the U634H256 performs a STORE

or RECALL.

w: E must be used to clock in the address sequence for the software controlled STORE and RECALL cycles.

April 21, 2004

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