SM8213 データシートの表示（PDF） - Nippon Precision Circuits

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SM8213

POCSAG Decoder For Multiframe Pagers

Nippon Precision Circuits  

BLOCK DIAGRAM

SM8213AM

VDD

BS1

Timing Control

Buffer Register

BS2

Flag Register

(Ring)

Buffer Register

BS3

Address Register

ATTN

SDI

SDO

SCK

SIGNAL

XVSS

XT

XTN

Receive Data Register Error Correction

Digital PLL Data Comparator

Preamble Pattern

Sync Code

Idle Code

Main Control

Circuit

Timer

AREA

Each Switch

and Register

RSTN

Clock Control

Each Working Block

CLKO

VSS

NIPPON PRECISION CIRCUITS—2

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