MSM9842 データシートの表示（PDF） - Oki Electric Industry
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MSM9842 Datasheet PDF : 9 Pages
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¡ Semiconductor
FEDL9842-02
MSM9842
PIN DESCRIPTIONS
Symbol Type
Description
For 8-bit bus interface, the command allows these pins to be configured to be inputs to input
D15-D8
data to and from an external memory. Otherwise, these pins are configured to be inputs only.
I/O
For 16-bit interface, these pins are a bidirectional data bus to input data to and from an external
microcontroller and memory.
D7-D0
Birirectional data bus to input data and output status to and from an external microcontroller
I/O
and memory.
WR
I Write pulse input pin. This pin pulses "L" when command or voice data is input to D15-D0 pins.
RD
I Read pulse input pin. This pin pulses "L" when status is output to D7-D0 pins.
CS
Accepts write pulse and read pulse when this pin is "L". Does not accept write pulse and read
I
pulse when this pin is "H".
D/C
Voice data is input to D15-D0 pins when this pin is "H". Command is input to and status is
I
output from D7-D0 pins when this pin is "L".
BUSY
O This pin outputs a "L" level during, PLAYBACK or PAUSE.
"H" level indicates that there is no data in FIFO memory. Active "H" can be changed to active "L"
EMP
O
by command input.
"H" level indicates that more than half of the FIFO memory space is filled with data.
Voice synthesis starts when MID changes to "H" level. Active "H" can be changed to active "L"
MID
O by command input. This pin outputs a synchro signal for voice data input when non-use of FIFO
is selected.
"H" level indicates that FIFO memory is full of data. This pin is "H" and data cannot be written in
FIFO memory. Active "H" can be changed to active "L" by command input.
FUL/DREQR O
When DMA transfer is selected, "H" level DREQR outputs a signal to request a DMA transfer.
Active "H" can be changed to active "L" by command input.
When stereo playback is selected and CH is "H", voice data is written in right FIFO memory, and
the EMP, MID or FUL pin outputs the status of right FIFO memory.
When CH is "L", data is written in right FIFO memory, and the EMP, MID or FUL pin outputs the
CH/DACKR I status of left FIFO memory. Set this pin to "L" during monophonic playback.
When DMA transfer and stereo playback are selected, DACKR is selected. In this case, DACKR
outputs a DMA transfer acknowledge signal. When DACKR is "L", the IOW signal is accepted.
Active "L" can be changed to active "H" by command input.
DREQL
When DMA transfer is selected, "H" level DREQL outputs a signal to request a DMA transfer.
O
Active "H" can be changed to active "L" by command input.
DACKL
DACKL inputs a signal when DMA transfer is permitted by the DMA controller. When DACKL
is "L", IOW signal is accepted. When stereo playback is selected, DACKL is a DMA transfer
I
acknowledge signal for left FIFO memory. Active "L" can be changed to active "H" by command
input. If DMA transfer is not used, set this pin to "H" level.
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