UCB1500 データシートの表示（PDF） - Philips Electronics

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UCB1500

PCI to AC97 bridge/host controller

Philips Electronics 

Philips Semiconductors

UCB1500

PCI to AC97 bridge/host controller

[05-04]: Command Register

Table 15: Command Register bit description

Bit

Description

15-10

Reserved.

9(r)

Fast Back-to-back Transactions

Always 0, fast back-to-back transactions is not supported.

8

SERR enable

If set, SERR driver is enabled; if 0, SERR is disabled.

7(r)

Address/Data Stepping

Always 0, address/data stepping is not implemented.

6

Parity Error Response

When set, the device must take its normal action when a parity error is detected.

If this bit is 0, the device must ignore any parity errors that it detects and continue

normal operation.

5(r)

VGA Snooping

Always 0, not implemented.

4(r)

Memory Write and Invalidate Command

Always 0, UCB1500 does not generate memory write and invalidate command.

3(r)

Special Cycle Response

Always 0, UCB1500 ignores all special cycles.

2

Bus Master Control

PCI Master access enable; this bit must be enabled to activate UCB1500 DMA

register.

1 = enable.

1(r)

Memory Space Response

Always 0, UCB1500 does not respond to memory space accesses.

0

I/O Space Control

UCB1500 control register I/O space access enable.

1 = enable.

9397 750 06854

Objective specification

Rev. 01 — 4 February 2000

© Philips Electronics N.V. 2000. All rights reserved.

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