Released PM7329 S/UNI-APEX-1K800
Packet/ATM Traffic Manager and Switch
CONGESTION CONTROL
• Traffic discard thresholds configurable
per connection (independent CLP0
and CLP1 thresholds), per class, per
port, and per direction.
• Guaranteed Frame Rate (GFR)
implemented via CLP0 minimum buffer
size reservation per connection.
QUEUING & SCHEDULING
• 1024 traffic staging queues (one per
connection) individually assignable to
any CoS on any port.
• 512 + 20 scheduling queues: 4 CoS
queues per port, 128 line ports, 4 WAN
ports, and 1 processor port.
• Each port’s queuing and scheduling is
configurable as cell at a time or packet
at a time.
• Connections are scheduled into each
class queue using configurable
weighted fair queuing (cell mode), or
FIFO (frame mode).
• Classes are scheduled into ports using
strict priority with configurable
minimum bandwidth reservation.
• Ports are scheduled onto their
corresponding bus using a
configurable weighted interleaved
round robin algorithm.
• On the WAN ports: rate shaping,
individually configured per connection,
within four classes.
ACCOUNTING
• Per connection CLP0/CLP1 upstream/
downstream Tx counts.
• Error statistics accumulation.
• CLP0/CLP1 cell discard counts with
indication of connection ID of last cell
discarded.
APPLICATIONS
• Mini Digital Subscriber Loop Access
Multiplexer (mini-DSLAM).
• Subscriber Access equipment.
• Digital Loop Card traffic aggregation.
TYPICAL APPLICATION
S/UNI-APEX-1K800 IN OC3 MINI-DSLAM APPLICATION
line cards
up to 31
Utopia
L2 ports
up to 31
Utopia
L2 ports
DSL PHY
DSL PHY
DSL PHY
DSL PHY
PM7350
S/UNI-
DUPLEX
line cards
PM7350
S/UNI-
DUPLEX
PM7351
S/UNI-
200
VORTEX
Mbit/s
LVDS
DUUPpLEtoX8dLeVvDicSeslinpkesr
tSo/USN/UI-NVIO- RTEX
Any-PHY/
SCI-PHY
PM7329
S/UNI-APEX-
1K800
PM7328
S/UNI-
ATLAS-
1K800
Context
SSRAM
Ingress
SSRAM
Packet/Cell
SDRAM
Egress
SSRAM
PHY
Host CPU
Core Card
S/UNI-APEX-1K800 IN OC3 DIGITAL LOOP CARD APPLICATION
line interface
Any-PHY/
SCI-PHY Bus
DSL PHY
DSL PHY
PM7329
S/UNI-APEX-
1K800
PM7328
S/UNI-ATLAS-
1K800
expansion
DSL PHY
Context
SSRAM
Ingress
SSRAM
Packet/Cell
SDRAM
Egress SSRAM
PHY
Host CPU
Digital Loop Card
Head Office:
PMC-Sierra, Inc.
#105 - 8555 Baxter Place
Burnaby, B.C. V5A 4V7
Canada
Tel: 604.415.6000
Fax: 604.415.6200
To order documentation,
send email to:
document@pmc-sierra.com
or contact the head office,
Attn: Document Coordinator
All product documentation is available
on our web site at:
http://www.pmc-sierra.com
For corporate information,
send email to:
info@pmc-sierra.com
PMC-2010038 (r3)
© Copyright PMC-Sierra, Inc. 2001. All
rights reserved. June 2001
S/UNI is a registered trademark of
PMC-Sierra, Inc.
Any-PHY and SCI-PHY are trademarks of
PMC-Sierra, Inc.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE