LC7471 データシートの表示（PDF） - SANYO -> Panasonic
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LC7471 Datasheet PDF : 12 Pages
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LC7471
RAM Memory Configuration
RAM memory is organized as 16-bit words as shown in
the following table. Locations 000H to 0AFH are display
RAM, locations 0B0H through to 0BBH are display line
address registers, locations 0BCH to 0BDH are display con-
trol registers, location 0BEH is the video signal control reg-
ister and location 0BFH is the general control register.
Memory contents
Address
F
EDCB
A
9
8
7
6
5
4
3
2
1
0
Description
000H to
0AFH
0
0
0
0
0
0
0
0
FL
0
C5
C4
C3
C2
C1
C0
Display RAM with 6-bit character
code and flashing enable bit
0B0H
0
0
0
0
0
Address in display ROM of first
ADRA ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 character of line 1
0B1H
0
0
0
0
0
Address in display ROM of first
ADRA ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 character of line 2
0B2H
0
0
0
0
0
Address in display ROM of first
ADRA ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 character of line 3
0B3H
0
0
0
0
0
Address in display ROM of first
ADRA ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 character of line 4
0B4H
0
0
0
0
0
Address in display ROM of first
ADRA ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 character of line 5
0B5H
0
0
0
0
0
Address in display ROM of first
ADRA ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 character of line 6
0B6H
0
0
0
0
0
Address in display ROM of first
ADRA ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 character of line 7
0B7H
0
0
0
0
0
Address in display ROM of first
ADRA ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 character of line 8
0B8H
0
0
0
0
0
Address in display ROM of first
ADRA ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 character of line 9
0B9H
0
0
0
0
0
Address in display ROM of first
ADRA ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 character of line 10
0BAH
0
0
0
0
0
Address in display ROM of first
ADRA ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 character of line 11
0BBH
0
0
0
0
0
Address in display ROM of first
ADRA ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0 character of line 12
0BCH 0
0
0
0
HSZ31 HSZ30 HSZ21 HSZ20 HSZ11 HSZ10 HP5
HP4
HP3
HP2
Hrizontal display start position and
HP1 HP0 pixel width
0BDH 0
0
0
0
VSZ31 VSZ30 VSZ21 VSZ20 VSZ11 VSZ10 VP5
VP4
VP3
VP2
VP1
Vertivcal display start position and
VP0 pixel height
Video signal phase, display
0BEH 0
0
0
0
INT/
NON
×
OSC DSP
SYS
×
STP ON
×
RST
×
×
× PH1 PH0 blanking, oscillator control and
system reset selection
0BFH
0
0
0
0
TST
MOD
×
×
BLK1 BLK0
×
Character blanking, flashing, and
FL2 FL1 FL0 EXT
×
BCOL test mode selection
Note
× = don’t care
Horizontal Display Control Register (0BCH)
The function of each bit in the horizontal display control register is shown in the following table. Note that a LOW-
level pulse on RST resets all bits to 0.
Data bit
Name
Function
0
HP0
1
HP1
Selects the horizontal start position of the display on the screen, HS, as given by the following equation
2
HP2
3
HP3
4
HP4
where TC is the period of the dot clock oscillator. Note that HS increments in multiples of 4TC.
5
HP5
6
HSZ10
Selects line 1 pixel width as shown in table 1.
7
HSZ11
8
HSZ20
Selects line 2 pixel width as shown in table 2.
9
HSZ21
A
HSZ30
Selects line 3 to line 12 pixel width as shown in table 3.
B
HSZ31
C
–
No function
Table 1. Line 1 pixel width
HSZ11 HSZ10
Width
0
0
0
1
1
0
1
1
1TC/pixel
2TC/pixel
3TC/pixel
4TC/pixel
Table 2. Line 2 pixel width
HSZ21 HSZ20
Width
0
0
0
1
1
0
1
1
1TC/pixel
2TC/pixel
3TC/pixel
4TC/pixel
Table 3. Line 3 to line 12 pixel width
HSZ31 HSZ30
Width
0
0
0
1
1
0
1
1
1TC/pixel
2TC/pixel
3TC/pixel
4TC/pixel
No.4088–5/12
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