IN74ACT374DW データシートの表示（PDF） - Integral Corp.

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IN74ACT374DW

Octal 3-state noninverting D flip-flop high-speed silicon-gate CMOS

Integral Corp. 

IN74ACT374

AC ELECTRICAL CHARACTERISTICS(VCC=5.0 V ± 10%, CL=50pF,Input tr=tf=3.0 ns)

Guaranteed Limits

Symbol

Parameter

25 °C

-40°C to

Unit

85°C

Min Max Min Max

fmax Maximum Clock Frequency (Figure 1)

100

90

MHz

tPLH Propagation Delay, Clock to Q (Figure 1) 2.0 10 2.0 11.5 ns

tPHL Propagation Delay, Clock to Q (Figure 1) 2.0 9.5 1.5 11

ns

tPZH Propagation Delay, Output Enable to Q 2.0 9.5 1.5 10.5 ns

(Figure 2)

tPZL Propagation Delay, Output Enable to Q 1.5 9.0 1.5 10.5 ns

(Figure 2)

tPHZ Propagation Delay, Output Enable to Q 1.5 11.5 1.0 12.5 ns

(Figure 2)

tPLZ Propagation Delay, Output Enable to Q 1.5 8.5 1.0 10

ns

(Figure 2)

CIN Maximum Input Capacitance

4.5

4.5

pF

CPD Power Dissipation Capacitance

Typical @25°C,VCC=5.0 V

80

pF

TIMING REQUIREMENTS (VCC=5.0 V ± 10%,(CL=50pF, Input tr=tf=3.0 ns)

Guaranteed Limits

Symbol

Parameter

25 °C

-40°C to Unit

85°C

tsu Minimum Setup Time,Data to Clock

5.0

(Figure 3)

5.5

ns

th Minimum Hold Time, Clock to Data

1.5

(Figure 3)

1.5

ns

tw Minimum Pulse Width, Clock (Figure 1)

5.0

5.0

ns

4

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