M40SZ100YMH データシートの表示（PDF） - STMicroelectronics

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M40SZ100YMH

5V or 3V NVRAM SUPERVISOR FOR LPSRAM

STMicroelectronics 

M40SZ100Y, M40SZ100W

Table 5. DC Characteristics

Sym

Parameter

Test Condition(1)

M40SZ100Y

Min Typ

Max

M40SZ100W

Unit

Min Typ Max

ICC Supply Current

Outputs open

1

0.5

mA

ICCDR

Data Retention Mode

Current(2)

50

200

50

200

nA

Input Leakage

ILI(3)

Current

Input Leakage

Current (PFI)

0V ≤ VIN ≤ VCC

–25

2

±1

25

–25

2

±1

µA

25

nA

ILO(4)

Output Leakage

Current

0V ≤ VOUT ≤ VCC

±1

±1

µA

IOUT1(5)

VOUT Current

(Active)

VOUT > VCC – 0.3

175

100

mA

IOUT2

VOUT Current

(Battery Back-up)

VOUT > VBAT – 0.3

100

100

µA

VBAT Battery Voltage

2.5

3.0

3.5(6)

2.5

3.0

3.5(6)

V

VIH Input High Voltage

0.7VCC

VCC + 0.3 0.7VCC

VCC + 0.3 V

VIL Input Low Voltage

–0.3

0.3VCC –0.3

0.3VCC V

VOH

Output High

Voltage(7)

IOH = –1.0mA

2.4

2.4

V

VOHB

VOH Battery Back-

up(8)

IOUT2 = –1.0µA

2.5

2.9

3.5

2.5 2.9

3.5

V

Output Low Voltage

IOL = 3.0mA

0.4

0.4

V

VOL Output Low Voltage

(open drain)(9)

IOL = 10mA

0.4

0.4

V

VPFD

Power-fail Deselect

Voltage

4.20 4.40 4.50

2.55 2.60 2.70

V

PFI Input Threshold

VPFI

PFI Hysteresis

VCC = 5V(Y)

VCC = 3V(V)

PFI Rising

1.225 1.250 1.275 1.225 1.250 1.275

V

20

70

20

70

mV

VSO

Battery Back-up

Switchover Voltage

2.5

2.5

V

Note: 1. Valid for Ambient Operating Temperature: TA = –40 to 85°C; VCC = 2.7 to 3.6V or 4.5 to 5.5V(except where noted).

2. Measured with VOUT and ECON open.

3. RSTIN internally pulled-up to VCC through 100kΩ resistor.

4. Outputs deselected.

5. External SRAM must match SUPERVISOR chip VCC specification (3V or 5V).

6. For rechargeable back-up, VBAT (max) may be considered VCC – 0.5V.

7. For PFO pin (CMOS).

8. Chip Enable output (ECON) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage currents will re-

duce battery life.

9. For RST & BL pins (Open Drain).

7/19

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