CXD2443Q
Pin
No.
Symbol
I/O
71 RSTR O
72 WCK O
73 RSTW O
74 CKO4 I/O
75 CKI4
I
76 RPD4 O
77 FPD4 O
78 VDD
—
79 VSS
—
80 PEO4 I/O
81 PWM4 O
82 TC4 I/O
83 TC2 I/O
84 FPD2 O
85 PEO2 I/O
86 PWM2 O
87 RPD2 O
88 CKO2 I/O
89 CKI2
I
90 VSS
—
91 CKO3 I/O
92 CKI3
I
93 RPD3 O
94 PEO3 I/O
95 PWM3 O
96 FPD3 O
97 TC3 I/O
98 CKSL I
99 CKI5
I
100 HDR O
Description
Input pin for
open status
Read reset output (for line buffer, negative polarity)
—
Write clock output (for line buffer)
—
Write reset output (for line buffer, negative polarity)
—
Oscillation cell 4 output (line double-speed controller)
—
Oscillation cell 4 input (line double-speed controller)
—
Phase comparator 4 output (line double-speed controller)
—
Phase comparator 4 output (line double-speed controller)
—
Power supply
—
GND
—
Loop filter integrator 4 output (line double-speed controller)
—
Loop filter integrator 4 input (line double-speed controller)
—
FPD4 output pulse width adjustment (line double-speed controller)
—
FPD2 output pulse width adjustment (NTSC/PAL 16:9)
—
Phase comparator 2 output (NTSC/PAL 16:9)
—
Loop filter integrator 2 output (NTSC/PAL 16:9)
—
Loop filter integrator 2 input (NTSC/PAL 16:9)
—
Phase comparator 2 output (NTSC/PAL 16:9)
—
Oscillation cell 2 output (NTSC/PAL 16:9)
—
Oscillation cell 2 input (NTSC/PAL 16:9)
—
GND
—
Oscillation cell 3 output (HD)
—
Oscillation cell 3 input (HD)
—
Phase comparator 3 output (HD)
—
Loop filter integrator 3 output (HD)
—
Loop filter integrator 3 input (HD)
—
Phase comparator 3 output (HD)
—
FPD3 output pulse width adjustment (HD)
—
PLL system switching (High: Built-in PLL, Low: External PLL)
H
External clock input (for external phase comparison)
—
Phase comparator output (for external phase comparison)
—
∗ H: Pull up, L: Pull down
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