C505L
Reset and System Clock
The reset input is an active high input at pin RESET. Since the reset is synchronized internally, the
RESET pin must be held low for at least two machine cycles (12 oscillator periods) while the
oscillator is running. A pull-down resistor is internally connected to VSS to allow a power-up reset
with an external capacitor only. An automatic reset can be obtained when VDD is applied by
connecting the RESET pin to VDD via a capacitor. Figure 6 shows the possible reset circuitries.
VDD a)
+
C505L
RESET
b)
C505L
&
RESET
VDD
Figure 6
Reset Circuitries
c)
C505L
RESET
+
MCS03840
Data Sheet
16
06.99