74LVC32A(2018) データシートの表示（PDF） - NXP Semiconductors.

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74LVC32A
(Rev.:2018)

Quad 2-input OR gate

NXP Semiconductors. 

Nexperia

74LVC32A

Quad 2-input OR gate

12. Abbreviations

Table 9. Abbreviations

Acronym

CDM

CMOS

DUT

ESD

HBM

MM

TTL

Description

Charged Device Model

Complementary Metal-Oxide Semiconductor

Device Under Test

ElectroStatic Discharge

Human Body Model

Machine Model

Transistor-Transistor Logic

13. Revision history

Table 10. Revision history

Document ID

74LVC32A v.6

Modifications:

74LVC32A v.5

Modifications:

74LVC32A v.4

74LVC32A v.3

74LVC32A v.2

74LVC32A v.1

Release date Data sheet status

20180912

Product data sheet

Change notice Supersedes

-

74LVC32A v.5

• The format of this data sheet has been redesigned to comply with the identity guidelines

of Nexperia.

• Legal texts have been adapted to the new company name where appropriate.

• Package outline drawing SOT762-1 updated.

• Typo corrected in tpd value: 1.05 ns to 1.5 ns.

20111117

Product data sheet

-

74LVC32A v.4

• Legal pages updated.

• Table 6, ΔICC: condition VCC changed.

20111019

Product data sheet

-

74LVC32A v.3

20030716

Product specification

-

74LVC32A v.2

19970630

Product specification

-

74LVC32A v.1

19970630

Product specification

-

-

74LVC32A

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 6 — 12 September 2018

© Nexperia B.V. 2018. All rights reserved

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