點晶科技股份有限公司
SILICON TOUCH TECHNOLOGY INC.
Timing Diagram
DM114、DM115
CLOCK
SERIAL IN
LATCH
ENABLE
OUT0
OUT1
OUT2
OUT7
SERIAL-OUT
3.3/5V
0V
3.3/5V
0V
3.3/5V
0V
3.3/5V
0V
Off
On
Off
Off
On
Off
3.3/5V
0V
(Note) Latches are level sensitive (not edge triggered).
LATCH-terminal = H level, latches become transparent; LATCH-terminal = L level, latches hold data.
ENABLE-terminal = H level, all outputs (OUT0~7) are off.
An external resistor is connected between R-EXT and GND for setting up the value of constant current.
SERIAL-OUT changes state on the rising edges of clock.
Pin Description
PIN No.
1
2
3
4
5~12
13
14
15
16
PIN NAME
GND
SERIAL-IN
CLOCK
LATCH
OUT0~7
ENABLE
SERIAL-OUT
R-EXT
VDD
FUNCTION
GND terminal
Input terminal of a data shift register
Input terminal of a clock for shift register
Input terminal for data strobe
Output terminals
Input terminal for output enable (active low)
Output terminal of a data shift register
Input terminal of an external resistor
3.3/5V Supply voltage terminal
8-BIT CONSTANT CURRENT LED DRIVERS with 3.3V~5V supply voltage
Preliminary
Version:A.002
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