MC74HC4017D データシートの表示（PDF） - Motorola => Freescale
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MC74HC4017D Datasheet PDF : 9 Pages
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MC74HC4017
TYPICAL APPLICATIONS
VCC
÷5
÷2
÷6
÷7
÷3
1 Q5 HC4017 VCC 16
2 Q1
RESET 15
3
Q0
CLOCK 14
4 Q2
5 Q6
CLOCK 13
ENABLE
CARRY OUT
12
÷ 10
6 Q7
Q9 11
÷9
7 Q3
Q4 10
÷4
8 GND
Q8 9
÷8
OSC.
(NO FEEDBACK REQUIRED)
1/6 HC04
OUTPUT
BUFFER
(OPTIONAL TO PREVENT SPURIOUS RESET.)
Figure 10 shows a divide by 2 through 10 circuit using one HC4017. Please note that since Reset is asynchronous, the
output pulse widths are narrow.
Figure 10. ÷2 Through ÷ 10 Circuit
R
C
HC4017
CE
Q0 Q1
Q8 Q9
C
CE
Q0 Q1
R
HC4017
Q8 Q9
R
C
CE HC4017
Q1
Q8 Q9
9 DECODED
OUTPUTS
8 DECODED
OUTPUTS
8 DECODED
OUTPUTS
CLOCK
FIRST STAGE
HC08
INTERMEDIATE STAGES
HC08
LAST STAGE
Figure 11 shows a technique for cascading the counters to extend the number of decoded output states. Decoded outputs
are sequential within each stage and from stage to stage, with no dead time (except propagation delay).
Figure 11. Counter Expansion
MOTOROLA
8
High–Speed CMOS Logic Data
DL129 — Rev 6
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