CMOS SyncBiFIFOTM WITH
BUS-MATCHING AND BYTE SWAPPING
64 x 36 x 2
IDT723614
FEATURES:
• Free-running CLKA and CLKB can be asynchronous or
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)
• Two independent clocked FIFOs (64 x 36 storage capacity each)
buffering data in opposite directions
• Mailbox bypass Register for each FIFO
• Dynamic Port B bus sizing of 36 bits (long word), 18 bits (word),
and 9 bits (byte)
• Selection of Big- or Little-Endian format for word and byte bus
sizes
• Three modes of byte-order swapping on port B
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor interface control logic
• EFA, FFA, AEA, and AFA flags synchronized by CLKA
• EFB, FFB, AEB, and AFB flags synchronized by CLKB
• Passive parity checking on each port
• Parity generation can be selected for each port
• Supports clock frequencies up to 67 MHz
• Fast access times of 10 ns
• Available in 132-pin plastic quad flat package (PQF) or space-
saving 120-pin thin quad flat package (TQFP)
• Industrial temperature range (–40°C to +85°C) is available
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
Mail 1
Register
Parity
Gen/Check
MBF1
PEFB
PGB
RST
ODD/
EVEN
Device
Control
FFA
AFA
36
FS0
FS1
A0 - A35
EFA
AEA
RAM
ARRAY
64 x 36
Write Read
Pointer Pointer
FIFO1
FIFO2
Status Flag
Logic
Programmable Flag
Offset Register
Status Flag
Logic
Read Write
Pointer Pointer
36
EFB
AEB
B0-B35
FFB
AFB
36
RAM
ARRAY
64 x 36
PGA
PEFA
MBF2
Parity
Gen/Check
Mail 2
Register
Port-B
Control
Logic
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBIFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
© 2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
CLKB
CSB
W/RB
ENB
BE
SIZ0
SIZ1
SW0
SW1
3146 drw01
MARCH 2002
DSC-3146/1