HN58C65P-25 データシートの表示（PDF） - Hitachi -> Renesas Electronics

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HN58C65P-25

8192-word × 8-bit Electrically Erasable and Programmable CMOS ROM

Hitachi -> Renesas Electronics 

HN58C65 Series

Write Cycle

Parameter

Symbol Min*1 Typ Max Unit Test Conditions

Address setup time

t AS

0

—

—

ns

Address hold time

t AH

150 —

—

ns

CE to write setup time (WE controlled) tCS

0

—

—

ns

CE hold time (WE controlled)

t CH

0

—

—

ns

WE to write setup time (CE controlled) tWS

0

—

—

ns

WE hold time (CE controlled)

t WH

0

—

—

ns

OE to write setup time

t OES

0

—

—

ns

OE hold time

t OEH

0

—

—

ns

Data setup time

t DS

100 —

—

ns

Data hold time

t DH

20

—

—

ns

WE pulse width (WE controlled)

t WP

200 —

—

ns

CE pulse width (CE controlled)

t CW

200 —

—

ns

Data latch time

t DL

100 —

—

ns

Byte lode cycle

t BLC

0.30 —

30

µs

Byte lode window

t BL

100 —

—

µs

Write cycle time

t WC

—

—

10*2

ms

Time to devce busy

t DB

120 —

—

ns

Write start time

t DW

150 —

—

ns

Notes: 1. Use this device in longer cycle than this value.

2. tWC must be longer than this value unless polling technique is used. This device automatically

completes the internal write operation within this value.

7

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