SL74HC597D データシートの表示（PDF） - System Logic Semiconductor
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SL74HC597D
System Logic Semiconductor
SL74HC597D Datasheet PDF : 9 Pages
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SL74HC597
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Symbol
Parameter
V
tsu
Minimum Setup Time, Parallel Data
2.0
Inputs A -H to Latch Clock
4.5
(Figure 5)
6.0
tsu
Minimum Setup Time, Serial Data
2.0
Input SA to Shift Clock (Figure 6)
4.5
6.0
tsu
Minimum Setup Time, Serial
2.0
Shift/Parallel Load to Shift Clock
4.5
(Figure 7)
6.0
th
Minimum Hold Time, Latch Clock to
2.0
Parallel Data Inputs A-H
4.5
(Figure 5)
6.0
th
Minimum Hold Time, Shift Clock to
2.0
Serial Data Input SA (Figure 6)
4.5
6.0
trec
Minimum Recovery Time, Reset
2.0
Inactive to Shift Clock (Figure 3)
4.5
6.0
tw
Minimum Pulse Width, Latch Clock
2.0
and Shift Clock (Figures 1 and 2)
4.5
6.0
tw
Minimum Pulse Width, Reset (Figure 2.0
3)
4.5
6.0
tw
Minimum Pulse Width, Serial
2.0
Shift/Parallel Load (Figure 4)
4.5
6.0
tr, tf Maximum Input Rise and Fall Times
2.0
(Figure 1)
4.5
6.0
Guaranteed Limit
25 °C to
-55°C
≤85°C ≤125°C Unit
100
125
150
ns
20
25
30
17
21
26
100
125
150
ns
20
25
30
17
21
26
100
125
150
ns
20
25
30
17
21
26
25
30
40
ns
5
6
8
5
6
7
5
5
5
ns
5
5
5
5
5
5
100
125
150
ns
20
25
30
17
21
26
80
100
120
ns
16
20
24
14
17
20
80
100
120
ns
16
20
24
14
17
20
80
100
120
ns
16
20
24
14
17
20
1000
1000
1000
ns
500
500
500
400
400
400
SLS
System Logic
Semiconductor
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