SL74HC165 データシートの表示（PDF） - System Logic Semiconductor
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SL74HC165
System Logic Semiconductor
SL74HC165 Datasheet PDF : 7 Pages
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SL74HC165
TIMING REQUIREMENTS (CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
VCC
Guaranteed Limit
V
25 °C to
≤85°C
≤125°C
Unit
-55°C
tSU
Minimum Setup Time, Parallel
2.0
100
125
150
ns
Data Inputs to Serial
4.5
20
25
30
Shift/Parallel Load (Figure 4)
6.0
17
21
26
tSU
Minimum Setup Time, Input SA 2.0
100
125
150
ns
to Clock (or Clock Inhibit)
4.5
20
25
30
(Figure 5)
6.0
17
21
26
tSU
Minimum Setup Time, Serial
2.0
100
125
150
ns
Shift/Parallel Load to Clock (or 4.5
20
25
30
Clock Inhibit) (Figure 6)
6.0
17
21
26
tSU
Minimum Setup Time, Clock to 2.0
100
125
150
ns
Clock Inhibit (Figure 7)
4.5
20
25
30
6.0
17
21
26
th
Minimum Hold Time, Serial
2.0
5
5
5
ns
Shift/Parallel Load to Parallel
4.5
5
5
5
Data Inputs (Figure 4)
6.0
5
5
5
th
Minimum Hold Time, Clock (or 2.0
5
5
5
ns
Clock Inhibit) to Input SA
4.5
5
5
5
(Figure 5)
6.0
5
5
5
th
Minimum Hold Time, Clock (or 2.0
5
5
5
ns
Clock Inhibit) to Serial
4.5
5
5
5
Shift/Parallel Load (Figure 6)
6.0
5
5
5
trec
Minimu m Recovery Time,
2.0
100
125
150
ns
Clock to Clock Inhibit
4.5
20
25
30
(Figure 7)
6.0
17
21
26
tw
Minimum Pulse Width, Clock
2.0
80
(or Clock Inhibit) (Figure 1)
4.5
16
6.0
14
100
120
ns
20
24
17
20
tw
Minimum Pulse Width, Serial
2.0
80
Shift/Parallel Load (Figure 2)
4.5
16
6.0
14
100
120
ns
20
24
17
20
tr, tf Maximum Input Rise and Fall
2.0
1000
1000
1000
ns
Times (Figure 1)
4.5
500
500
500
6.0
400
400
400
SLS
System Logic
Semiconductor
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