MIC4690
To minimize stray inductance and ground loops, keep trace
lengths, indicated by the heavy lines in Figure 5, as short as
possible. For example, keep D1 close to pin 3 and pins 5
through 8, keep L1 away from sensitive node FB, and keep
CIN close to pin 2 and pins 5 though 8. See “Applications
Information: Thermal Considerations” for ground plane lay-
out.
Micrel
The feedback pin should be kept as far way from the switching
elements (usually L1 and D1) as possible.
A circuit with sample layouts are provided. See Figures 6a
though 6e. Gerber files are available upon request.
VIN
+4V to +30V
(34V transients)
CIN
Power
SOP-8
MIC4690BM
2
VIN
3
SW
1
SHDN
4
FB
GND
5678
L1
D1
VOUT
COUT
R1
R2
GND
Figure 5. Critical Traces for Layout
J1
VIN
4V to +30V
(34V transients)
C1
22µF
35V
J3
GND
OFF
C2
0.1µF
50V
ON
JP1
U1 MIC4690BM
2
IN
3
SW
1
SHDN
4
FB
SOP-8
GND
5Ð8
* C3 can be used to provide additional stability
and improved transient response.
L1
18µH
R1
3.01k
C3* 1800pF / 50V
optional
D1
2A
40V
R6
optional
1
2
R2
6.49k
3
JP2a
1.8V
4
R3
2.94k
5
JP2b
2.5V
6
R4
1.78k
7
JP2c
3.3V
8
R5
976½
JP2d
5.0V
Figure 6a. Evaluation Board Schematic Diagram
C4
220µF
10V
J2
VOUT
1A
C5
0.1µF
50V
J4
GND
MIC4690
10
June 2001