74HC/HCT162 データシートの表示（PDF） - Philips Electronics

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74HC/HCT162

Presettable synchronous BCD decade counter; synchronous reset

Philips Electronics 

Philips Semiconductors

Presettable synchronous BCD decade

counter; synchronous reset

Product specification

74HC/HCT162

The shaded areas indicate when the input is permitted to

change for predictable output performance.

(1) HC : VM = 50%; VI = GND to VCC.

HCT : VM = 1.3 V; VI = GND to 3 V.

Fig.11 Waveforms showing the MR set-up and hold times.

The shaded areas indicate when the input is permitted

to change for predictable output performance.

(1) HC : VM = 50%; VI = GND to VCC.

HCT : VM = 1.3 V; VI = GND to 3 V.

Fig.12 Waveforms showing the CEP and CET set-up and hold times.

APPLICATION INFORMATION

The HC/HCT162 facilitate designing counters of any modulus with minimal external logic.

The output is glitch-free due to the synchronous reset.

Fig.13 Modulo-5 counter.

PACKAGE OUTLINES

See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.

December 1990

11

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