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MAX17480GTL データシートの表示(PDF) - Maxim Integrated

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MAX17480GTL Datasheet PDF : 48 Pages
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AMD 2-/3-Output Mobile Serial
VID Controller
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VIN = 12V, VCC = VDD = VIN3 = SHDN = PGD_IN = 5V, VDDIO = 1.8V, OPTION = GNDS_ = AGND = PGND,
FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, TA = 0°C to +85°C, unless otherwise noted.
Typical values are at TA = +25°C.)
PARAMETER
FAULT DETECTION
Output Overvoltage Trip
Threshold
(SMPS1 and SMPS2 Only)
Output Overvoltage Fault
Propagation Delay (SMPS1 and
SMPS2 Only)
Output Undervoltage Protection
Trip Threshold
Output Undervoltage Fault
Propagation Delay
PWRGD Threshold
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
PWM mode
250 300 350
mV
Skip mode and output
Measured at
has not reached the
1.80 1.85 1.90
VOVP_
FBDC_, rising
edge
regulation voltage
V
Minimum OVP
0.8
threshold
tOVP FBDC_ forced 25mV above trip threshold
10
µs
VUVP
Measured at FBDC_ or OUT3 with respect
to unloaded output voltage
-450
-400
-350
mV
tUVP FBDC_ forced 25mV below trip threshold
10
µs
Measured at
FBDC_ or OUT3
with respect to
unloaded output
voltage,15mV
hysteresis (typ)
Lower threshold,
falling edge
(undervoltage)
Upper threshold,
rising edge
(overvoltage)
-350 -300 -250
mV
+150 +200 +250
PWRGD Propagation Delay
tPWRGD
FBDC_ or OUT3 forced 25mV outside the
PWRGD trip thresholds
10
µs
PWRGD, Output Low Voltage
PWRGD Leakage Current
IPWRGD
ISINK = 4mA
High state, PWRGD forced to 5.5V,
TA = +25°C
0.4
V
1
µA
PWRGD Startup Delay and
Transition Blanking Time
tBLANK
Measured from the time when FBDC_ and
OUT3 reach the target voltage
20
µs
VRHOT Trip Threshold
VRHOT Delay
VRHOT, Output Low Voltage
VRHOT Leakage Current
THRM Input Leakage
Thermal-Shutdown Threshold
GATE DRIVERS
Measured at THRM, with respect to VCC,
29.5
30
30.5
%
falling edge, 115mV hysteresis (typ)
tVRHOT
THRM forced 25mV below the VRHOT trip
threshold, falling edge
10
µS
ISINK = 4mA
High state, VRHOT forced to 5V, TA = +25°C
0.4
V
1
µA
TA = +25°C
-100
+100
nA
TSHDN Hysteresis = 15°C
+160
°C
DH_ Gate-Driver On-Resistance
RON(DH_)
BST_ - LX_ forced
to 5V (Note 4)
High state (pullup)
Low state (pulldown)
0.9
2.5

0.7
2.5
DL_ Gate-Driver On-Resistance
DL_, high state
RON(DL_)
DL_, low state
0.7
2.0

0.25 0.6
_______________________________________________________________________________________ 5

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