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74LVQ373M データシート - STMicroelectronics

部品番号コンポーネント説明メーカー
74LVQ373M OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS NON INVERTING ST-Microelectronics
STMicroelectronics ST-Microelectronics
74LVQ373M PDF データシート : 74LVQ373M pdf   
74LVQ373M image

DESCRIPTION
The LVQ373 is a low voltage CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.It is ideal for low power and low noise 3.3V applications.
These 8 bit D-Type latchs are controlled by a latch enable input (LE) and an output enable input (OE).
While the LE input is held at a high level, the Q outputs will follow the data input precisely.
When the LE is taken low, the Q outputs will be latched precisely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state.
It has better speed performance at 3.3V than 5V LS-TTL family combined with the true CMOS low power consuption.
All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.

■ HIGH SPEED: tPD = 6 ns (TYP.) at VCC = 3.3V
■ COMPATIBLEWITH TTL OUTPUTS
■ LOW POWER DISSIPATION:
   ICC =4 µA (MAX.) at TA = 25 °C
■ LOW NOISE: VOLP = 0.4V(TYP.) at VCC = 3.3V
■ 75Ω TRANSMISSIONLINE OUTPUT DRIVE CAPABILITY
■ SYMMETRICAL OUTPUT IMPEDANCE:
   |IOH| = IOL = 12 mA (MIN)
■ PCI BUS LEVELSGUARANTEED AT 24mA
■ BALANCEDPROPAGATIONDELAYS: tPLH ≅ tPHL
■ OPERATING VOLTAGERANGE:
   VCC (OPR)= 2V to 3.6V (1.2VData Retention)
■ PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373
■ IMPROVED LATCH-UP IMMUNITY


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