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SN74GTLPH16612 Datasheet PDF - Texas Instruments

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SN74GTLPH16612 Datasheet PDF : SN74GTLPH16612 pdf   
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The SN74GTLPH16612 is a medium-drive, 18-bit UBT (universal bus transceiver) that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, or clock-enabled modes of data transfer. This device provides a high-speed interface between cards operating at LVTTL logic levels and backplanes operating at GTLP signal levels. High-speed (about two times faster than standard LVTTL or TTL) backplane operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and OEC (output edge control). These improvements minimize bus settling time and have been designed and tested using several backplane models.

● Members of the Texas Instruments (TI™) Widebus™ Family
● UBT™ (Universal Bus Transceiver)
   Combines D-Type Latches and D-Type
   Flip-Flops for Operation in Transparent,
   Latched, Clocked, or Clock-Enabled Mode
● Translate Between GTLP Signal Levels and LVTTL Logic Levels
● Support Mixed-Mode (3.3 V and 5 V) Signal
   Operation on A-Port and Control Inputs
● B-Port Transition Time Optimized for Distributed Backplane Loads
● Ioff Supports Partial-Power-Down Mode Operation
● Bus Hold on A-Port Inputs Eliminates the
   Need for External Pullup/Pulldown
● Distributed VCC and GND Pins Minimize
   High-Speed Switching Noise
● ESD Protection Exceeds JESD 22
   – 2000-V Human-Body Model (A114-A)
   – 200-V Machine Model (A115-A)
   – 1000-V Charged-Device Model (C101)
● Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
● Package Options Include Plastic Shrink
   Small-Outline (DL), and Thin Shrink
   Small-Outline (DGG) Packages

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